The present disclosure relates generally to electrostatic discharge (ESD) protection and, more specifically, to an improved transistor for use in an ESD circuit. The improved transistor will also provide a more robust ESD performance when used in circuitry not directly related to ESD protection.
For processes that use LOCOS (localized oxidation of silicon), shallow or deep trench isolation and other methods to define active device regions, defects occur at the edge of the isolation. As illustrated in FIG. 1 where LOCOS isolation is used as an example, a substrate 10 has a nitride mask 14 separated from the surface of the substrate 10 by an oxide layer 12. The substrate 10 is subject to an oxidizing atmosphere, and local oxidation of the exposed surface of the oxide layer 12 grows to produce LOCOS region 16, as shown in FIG. 2. A bird's beak portion 18 extends under the nitride mask 14. The area within the edge of the bird's beak portion 18 of the LOCOS 16 defines a device region 20.
There are several defects that are produced during LOCOS processing. A “white ribbon” occurs when the silicon near the bird's beak 18 becomes nitrified and results in a weakness in the oxide growing over that region during subsequent processing. This defect is well understood and effectively eliminated in improved LOCOS processing.
A second defect is a stress-related defect. This occurs when certain combinations of nitride 14 thickness, oxide 12 thickness and the LOCOS operating conditions are utilized. Generally, thick nitrides 14 cause stress at the bird's beak 18 during oxidation. This can produce dislocations in the silicon or substrate 10 below the bird's beak region 18. It is very difficult to completely remove this stress-related defect. Likewise for other types of device isolation such as deep or shallow trench, there are stress-related and processing-related defects.
These dislocations are believed to cause accelerated diffusion of impurities which form the source and drain region under bird's beak 18 and the LOCOS 16. An insulated gate field effect transistor (IGFET) of the prior art is illustrated in FIG. 3 as including a gate 22 separated from the surface of the substrate 10 by an insulative layer of oxide 21. The gate 22 is used as a diffusion mask to form a self-aligned source region 24 and drain region 26. As illustrated by the dashed lines, the dislocation causes diffusion of the source and drain regions under the bird's beak 18 and the LOCOS 16. The lateral diffusion is also illustrated in FIG. 4, which shows four different gates separating three sources 24 from two drains 26.
In a normal operation of the IGFET, the biasing of the gate causes an inversion of the channel region 28 to form a conduction path between the source and drains.
Generally, a parasitic bipolar transistor formed between the source and drain regions and the uninverted portion of the substrate 10 will have little effect on the normal operation of the field effect transistor. When the field effect transistor is used as an ESD protection device, the parasitic bipolar transistor can be utilized to create a snapback characteristic that is advantageous for some types of ESD protection. However, portions of the source and drain regions 24, 26 which are below the bird's beak 18 in the dislocation area have a lower threshold and turn on first. This is an undesirable effect.
Another condition which lowers the resistance and the there by the threshold at the edge is formation of metal silicides. The application of metal contact to the source and drain regions 24, 26 and/or to the gate 22 or metal gates form metal silicides. This in combination with the dislocation area allows, in some instances, the portions of the source and drain regions 24, 26 which are below the bird's beak 18 in the dislocation area to turn on first. This is caused by the silicide processing that can cause the silicide to ‘decorate’ the defect.
The present IGFET minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region. The second gate portion or barrier extends sufficiently into the substrate region to space the width of the channel from the adjacent edge of the opening in the oxide.
The present device can be used in an ESD circuit in an integrated circuit. It may be connected with its source and drain regions between the supply terminals of the integrated circuit. It may also be connected to the input terminal and one of the supply terminals by itself or as part of a silicon controlled rectifier structure.
These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings.